Publications

2023

Ya Li, Jing-Hao Luo, Qing-Yun Dai, Jason K. Eshraghian, Bingo Wing-Kuen Ling, Ciyan Zheng, Xiao-Li Wang, A deep learning approach to cardiovascular disease classification using empirical mode decomposition for ECG feature extraction. Biomed. Signal Process. Control. 79(Part), 104188, 2023.
Farhad Modaresi, Matthew Guthaus, Jason K. Eshraghian, OpenSpike: An OpenRAM SNN Accelerator. CoRR abs/2302.01015, 2023.
Jason Yik, Soikat Hasan Ahmed, Zergham Ahmed, Brian Anderson, Andreas G. Andreou, Chiara Bartolozzi, Arindam Basu, Douwe den Blanken, Petrut Bogdan, Sander M. Bohté, Younes Bouhadjar, Sonia M. Buckley, Gert Cauwenberghs, Federico Corradi, Guido de Croon, Andreea Danielescu 0001, Anurag Reddy Daram, Mike Davies, Yigit Demirag, Jason Eshraghian, Jeremy Forest, Steve B. Furber, Michael Furlong, Aditya Gilra, Giacomo Indiveri, Siddharth Joshi, Vedant Karia, Lyes Khacef, James C. Knight, Laura Kriener, Rajkumar Kubendran, Dhireesha Kudithipudi, Gregor Lenz, Rajit Manohar, Christian Mayr 0001, Konstantinos P. Michmizos 0001, Dylan R. Muir, Emre Neftci, Thomas Nowotny, Fabrizio Ottati, Ayça Özcelikkale, Noah Pacik-Nelson, Priyadarshini Panda, Pao-Sheng Sun, Melika Payvand, Christian Pehle, Mihai A. Petrovici, Christoph Posch, Alpha Renner, Yulia Sandamirskaya, Clemens JS Schaefer, André van Schaik, Johannes Schemmel, Catherine D. Schuman, Jae-sun Seo, Sumit Bam Shrestha, Manolis Sifalakis, Amos Sironi, Kenneth Stewart, Terrence C. Stewart, Philipp Stratmann, Guangzhi Tang, Jonathan Timcheck, Marian Verhelst, Craig M. Vineyard, Bernhard Vogginger, Amirreza Yousefzadeh, Biyan Zhou, Fatima Tuz Zohora, Charlotte Frenkel, Vijay Janapa Reddi, NeuroBench: Advancing Neuromorphic Computing through Collaborative, Fair and Representative Benchmarking. CoRR abs/2304.04640, 2023.
Yikai Yang, Jason K. Eshraghian, Nhan Duy Truong, Armin Nikpour, Omid Kavehei, Neuromorphic deep spiking neural networks for seizure detection. Neuromorph. Comput. Eng. 3(1), 14010, 2023.
Rui-Jie Zhu, Qihang Zhao, Jason K. Eshraghian, SpikeGPT: Generative Pre-trained Language Model with Spiking Neural Networks. CoRR abs/2302.13939, 2023.
Ziyu Wang, Yuting Wu, Yongmo Park, Sangmin Yoo, Xinxin Wang, Jason K. Eshraghian, Wei D. Lu, PowerGAN: A Machine Learning Approach for Power Side-Channel Attack on Compute-in-Memory Accelerators. CoRR abs/2304.11056, 2023.
Samuel Schmidgall, Jascha Achterberg, Thomas Miconi, Louis Kirsch, Rojin Ziaei, S. Pardis Hajiseyedrazi, Jason Eshraghian, Brain-inspired learning in artificial neural networks: a review. CoRR abs/2305.11252, 2023.
Colin Drewes, Olivia Weng, Keegan Ryan, Bill Hunter, Christopher McCarty, Ryan Kastner, Dustin Richmond, Turn on, Tune in, Listen up: Maximizing Side-Channel Recovery in Time-to-Digital Converters. FPGA, 111-122, 2023.
Colin Drewes, Olivia Weng, Andres Meza, Alric Althoff, David Kohlbrenner, Ryan Kastner, Dustin Richmond, Pentimento: Data Remanence in Cloud FPGAs. CoRR abs/2303.17881, 2023.
Lin Cheng, Max Ruttenberg, Dai Cheol Jung, Dustin Richmond, Michael B. Taylor, Mark Oskin, Christopher Batten, Beyond Static Parallel Loops: Supporting Dynamic Task Parallelism on Manycore Architectures with Software-Managed Scratchpad Memories. ASPLOS (3), 46-58, 2023.
Sheng-Hong Wang, Hunter James Coffman, Kenneth Mayer, Sakshi Garg, Jose Renau, A Multi-threaded Fast Hardware Compiler for HDLs. CC, 25-36, 2023.
Haoyuan Wang, Scott Beamer, RepCut: Superlinear Parallel RTL Simulation with Replication-Aided Partitioning. ASPLOS (3), 572-585, 2023.

2022

Tanvir Ahmed Khan, Muhammed Ugur, Krishnendra Nathella, Dam Sunwoo, Heiner Litz, Daniel A. Jiménez, Baris Kasikci, Whisper: Profile-Guided Branch Misprediction Elimination for Data Center Applications. MICRO, 19-34, 2022.
Pu Li, Xiaoyuan Wang, Xue Zhang, Jason Kamran Eshraghian, Herbert Ho-Ching Lu, Spice modelling of a tri-state memristor and analysis of its series and parallel characteristics. IET Circuits Devices Syst. 16(1), 81-91, 2022.
Jason Kamran Eshraghian, Corey Lammie, Mostafa Rahimi Azghadi, Wei D. Lu, Navigating Local Minima in Quantized Spiking Neural Networks. CoRR abs/2202.07221, 2022.
Yuxuan Zhang, Tanvir Ahmed Khan, Gilles Pokam, Baris Kasikci, Heiner Litz, Joseph Devietti, OCOLOS: Online COde Layout OptimizationS. MICRO, 530-545, 2022.
Colleen Josephson, Weitao Shuai, Gabriel Marcano, Pat Pannuto, Josiah D. Hester, George Wells, The Future of Clean Computing May Be Dirty. GetMobile Mob. Comput. Commun. 26(3), 9-15, 2022.
Ciyan Zheng, Long Peng, Jason K. Eshraghian, Xiao-Li Wang, Jian Cen, Herbert Ho-Ching Iu, Spiking Neuron Implementation Using a Novel Floating Memcapacitor Emulator. Int. J. Bifurc. Chaos 32(15), 2250224:1-2250224:17, 2022.
Jason Kamran Eshraghian, Corey Lammie, Mostafa Rahimi Azghadi, Wei D. Lu, Navigating Local Minima in Quantized Spiking Neural Networks. AICAS, 352-355, 2022.
Corey Lammie, Jason Kamran Eshraghian, Chenqi Li, Amirali Amirsoleimani, Roman Genov, Wei D. Lu, Mostafa Rahimi Azghadi, Design Space Exploration of Dense and Sparse Mapping Schemes for RRAM Architectures. CoRR abs/2201.06703, 2022.
Peng Zhou, Jason Kamran Eshraghian, Dong-Uk Choi, Wei D. Lu, Sung-Mo Kang, Gradient-based Neuromorphic Learning on Dynamical RRAM Arrays. CoRR abs/2206.12992, 2022.
Ziyao Zhang, Maria Sabrina Ma, Jason Kamran Eshraghian, Daniele Vigolo, Ken-Tye Yong, Omid Kavehei, Work in Progress: Neuromorphic Cytometry, High-throughput Event-based flow Flow-Imaging. EBCCSP, 1-5, 2022.
Mohammed E. Elbtity, Peyton Chandarana, Brendan Reidy, Jason Kamran Eshraghian, Ramtin Zand, APTPU: Approximate Computing Based Tensor Processing Unit. IEEE Trans. Circuits Syst. I Regul. Pap. 69(12), 5135-5146, 2022.
Heiner Litz, Javier Gonzalez, Ana Klimovic, Christos Kozyrakis, RAIL: Predictable, Low Tail Latency for NVMe Flash. ACM Trans. Storage 18(1), 5:1-5:21, 2022.
John Madden, Gabriel Marcano, Stephen Taylor, Pat Pannuto, Colleen Josephson, Hardware to Enable Large-Scale Deployment and Observation of Soil Microbial Fuel Cells. SenSys, 906-912, 2022.
Pao-Sheng Vincent Sun, Alexander Titterton, Anjlee Gopiani, Tim Santos, Arindam Basu, Wei D. Lu, Jason Kamran Eshraghian, Intelligence Processing Units Accelerate Neuromorphic Learning. CoRR abs/2211.10725, 2022.
Alexander Henkes, Jason K. Eshraghian, Henning Wessels, Spiking neural networks for nonlinear regression. CoRR abs/2210.03515, 2022.
Shixin Song, Tanvir Ahmed Khan, Sara Mahdizadeh-Shahri, Akshitha Sriraman, Niranjan K. Soundararajan, Sreenivas Subramoney, Daniel A. Jiménez, Heiner Litz, Baris Kasikci, Thermometer: profile-guided btb replacement for data center applications. ISCA, 742-756, 2022.
Sami Barchid, José Mennesson, Jason Eshraghian, Chaabane Djeraba, Mohammed Bennamoun, Spiking Neural Networks for Frame-based and Event-based Single Object Localization. CoRR abs/2206.06506, 2022.
Xiaoyuan Wang, Chuan-Tao Dong, Pengfei Zhou, Sanjoy Kumar Nandi, Shimul Kanti Nath, Robert Glen Elliman, Herbert Ho-Ching Iu, Sung-Mo Steve Kang, Jason Kamran Eshraghian, Low-Variance Memristor-Based Multi-Level Ternary Combinational Logic. IEEE Trans. Circuits Syst. I Regul. Pap. 69(6), 2423-2434, 2022.
Xiaoyuan Wang, Zhiru Wu, Pengfei Zhou, Herbert Ho-Ching Iu, Sung-Mo Kang, Jason Kamran Eshraghian, FPGA Synthesis of Ternary Memristor-CMOS Decoders for Active Matrix Microdisplays. IEEE Trans. Circuits Syst. I Regul. Pap. 69(9), 3501-3511, 2022.
Peng Zhou, Dong-Uk Choi, Jason Kamran Eshraghian, Sung-Mo Kang, A Fully Memristive Spiking Neural Network with Unsupervised Learning. ISCAS, 634-638, 2022.
Gabriel Marcano, Colleen Josephson, Pat Pannuto, Early Characterization of Soil Microbial Fuel Cells. ISCAS, 1362-1366, 2022.
Jason Kamran Eshraghian, Wei D. Lu, The fine line between dead neurons and sparsity in binarized spiking neural networks. CoRR abs/2201.11915, 2022.
Saba Jamilan, Tanvir Ahmed Khan, Grant Ayers, Baris Kasikci, Heiner Litz, APT-GET: profile-guided EuroSys, 747-764, 2022.
Peng Zhou, Donguk Choi, Jason Kamran Eshraghian, Sung-Mo Steve Kang, A Fully Memristive Spiking Neural Network with Unsupervised Learning. CoRR abs/2203.01416, 2022.
Peng Zhou, Jason Kamran Eshraghian, Dong-Uk Choi, Sung-Mo Kang, SPICEprop: Backpropagating Errors Through Memristive Spiking Neural Networks. CoRR abs/2203.01426, 2022.
Ziyu Wang, Fan-Hsuan Meng, Yongmo Park, Jason Kamran Eshraghian, Wei D. Lu, Side-channel attack analysis on in-memory computing architectures. CoRR abs/2209.02792, 2022.
Devashish R. Purandare, Peter Wilcox, Heiner Litz, Shel Finkelstein, Append is Near: Log-based Data Management on ZNS SSDs. CIDR, 2022.
Corey Lammie, Jason Kamran Eshraghian, Chenqi Li, Amirali Amirsoleimani, Roman Genov, Wei D. Lu, Mostafa Rahimi Azghadi, Design Space Exploration of Dense and Sparse Mapping Schemes for RRAM Architectures. ISCAS, 1107-1111, 2022.
Lin Cheng, Peitian Pan, Zhongyuan Zhao 0004, Krithik Ranjan, Jack Weber, Bandhav Veluri, Seyed Borna Ehsani, Max Ruttenberg, Dai Cheol Jung, Preslav Ivanov, Dustin Richmond, Michael B. Taylor, Zhiru Zhang, Christopher Batten, A Tensor Processing Framework for CPU-Manycore Heterogeneous Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(6), 1620-1635, 2022.
Heiner Litz, Grant Ayers, Parthasarathy Ranganathan, CRISP: critical slice prefetching. ASPLOS, 300-313, 2022.
Peng Zhou, Dong-Uk Choi, Wei D. Lu, Sung-Mo Steve Kang, Jason Kamran Eshraghian, Gradient-Based Neuromorphic Learning on Dynamical RRAM Arrays. IEEE J. Emerg. Sel. Topics Circuits Syst. 12(4), 888-897, 2022.
Yikai Yang, Nhan Duy Truong, Jason Kamran Eshraghian, Christina Maher, Armin Nikpour, Omid Kavehei, A Multimodal AI System for Out-of-Distribution Generalization of Seizure Identification. IEEE J. Biomed. Health Informatics 26(7), 3529-3538, 2022.

2021

Dennis Robey, Wesley Thio, Herbert H. C. Iu, Jason Kamran Eshraghian, Naturalizing Neuromorphic Vision Event Streams Using GANs. CoRR abs/2102.07243, 2021.
Jason Kamran Eshraghian, Kyoungrok Cho, Sung Mo Kang, A 3-D Reconfigurable RRAM Crossbar Inference Engine. ISCAS, 1-5, 2021.
Niranjan K. Soundararajan, Peter Braun 0005, Tanvir Ahmed Khan, Baris Kasikci, Heiner Litz, Sreenivas Subramoney, PDede: Partitioned, Deduplicated, Delta Branch Target Buffer. MICRO, 779-791, 2021.
Mustafa S. Gobulukoglu, Colin Drewes, Bill Hunter, Dustin Richmond, Ryan Kastner, Classifying Computations on Multi-Tenant FPGAs. FPGA, 227, 2021.
David R. Ditzel, Roger Espasa, Nivard Aymerich, Allen Baum, Tom Berg, Jim Burr, Eric Hao, Jayesh Iyer, Miquel Izquierdo, Shankar Jayaratnam, Darren Jones, Chris Klingner, Jin Kim, Stephen Lee, Marc Lupon, Grigorios Magklis, Bojan Maric, Rajib Nath, Mike Neilly, J. Duane Northcutt, Bill Orner, Jose Renau, Gerard Reves, Xavier Reves, Tom Riordan, Pedro Sanchez, Sridhar Samudrala, Guillem Sole, Raymond Tang, Tommy Thorn, Francisco Torres, Sebastia Tortella, Daniel Yau, Accelerating ML Recommendation with over a Thousand RISC-V/Tensor Processors on Esperanto’s ET-SoC-1 Chip. HCS, 1-23, 2021.
Colin Drewes, Steven Harris, Winnie Wang, Richard Appen, Olivia Weng, Ryan Kastner, William Hunter, Christopher McCarty, Dustin Richmond, A Tunable Dual-Edge Time-to-Digital Converter. FCCM, 253, 2021.
Seongwon You, Jason Kamran Eshraghian, Herbert H. C. Iu, Kyoungrok Cho, Low-Power Wireless Sensor Network Using Fine-Grain Control of Sensor Module Power Mode. Sensors 21(9), 3198, 2021.
Jason Kamran Eshraghian, Kyoungrok Cho, Sung Mo Kang, CrossStack: A 3-D Reconfigurable RRAM Crossbar Inference Engine. CoRR abs/2102.06536, 2021.
Saeed Kargar, Heiner Litz, Faisal Nawab, Predict and Write: Using K-Means Clustering to Extend the Lifetime of NVM Storage. ICDE, 768-779, 2021.
Dan Iorga, Alastair F. Donaldson, Tyler Sorensen 0001, John Wickerson, The semantics of shared memory in Intel CPU/FPGA systems. Proc. ACM Program. Lang. 5(OOPSLA), 1-28, 2021.
Dennis E. Robey, Wesley Thio, Herbert H. C. Iu, Jason Kamran Eshraghian, Naturalizing Neuromorphic Vision Event Streams Using Generative Adversarial Networks. ISCAS, 1-5, 2021.
Tanvir Ahmed Khan, Dexin Zhang, Akshitha Sriraman, Joseph Devietti, Gilles Pokam, Heiner Litz, Baris Kasikci, Ripple: Profile-Guided Instruction Cache Replacement for Data Center Applications. ISCA, 734-747, 2021.
Seungbum Baek, Guk-Hyeon Yu, Jaewoo Kim, Chi Trung Ngo, Jason Kamran Eshraghian, Jong-Phil Hong, A Reconfigurable SRAM Based CMOS PUF With Challenge to Response Pairs. IEEE Access 9, 79947-79960, 2021.
Ajay Brahmakshatriya, Emily Furst, Victor A. Ying, Claire Hsu, Changwan Hong, Max Ruttenberg, Yunming Zhang, Dai Cheol Jung, Dustin Richmond, Michael B. Taylor, Julian Shun, Mark Oskin, Daniel Sánchez 0003, Saman P. Amarasinghe, Taming the Zoo: The Unified GraphIt Compiler Framework for Novel Architectures. ISCA, 429-442, 2021.
Amogh Lonkar, Scott Beamer, Accelerating Clique Counting in Sparse Real-World Graphs via Communication-Reducing Optimizations. CoRR abs/2112.10913, 2021.
Aninda Manocha, Tyler Sorensen 0001, Esin Tureci, Opeoluwa Matthews, Juan L. Aragón, Margaret Martonosi, GraphAttack: Optimizing Data Supply for Graph Applications on In-Order Multicore Architectures. ACM Trans. Archit. Code Optim. 18(4), 53:1-53:26, 2021.
Mustafa S. Gobulukoglu, Colin Drewes, William Hunter, Ryan Kastner, Dustin Richmond, Classifying Computations on Multi-Tenant FPGAs. DAC, 1261-1266, 2021.
Coen Arrow, Hancong Wu, Seungbum Baek, Herbert H. C. Iu, Kianoush Nazarpour, Jason Kamran Eshraghian, Prosthesis Control Using Spike Rate Coding in the Retina Photoreceptor Cells. ISCAS, 1-5, 2021.
Jason Kamran Eshraghian, Max Ward 0001, Emre Neftci, Xinxin Wang, Gregor Lenz, Girish Dwivedi, Mohammed Bennamoun, Doo Seok Jeong, Wei D. Lu, Training Spiking Neural Networks Using Lessons From Deep Learning. CoRR abs/2109.12894, 2021.
Corey Lammie, Jason Kamran Eshraghian, Wei D. Lu, Mostafa Rahimi Azghadi, Memristive Stochastic Computing for Deep Learning Parameter Optimization. IEEE Trans. Circuits Syst. II Express Briefs 68(5), 1650-1654, 2021.
Peter Wilcox, Heiner Litz, Design for computational storage simulation platform. CHEOPS@EuroSys, 5:1-5:8, 2021.
Nursultan Kabylkas, Tommy Thorn, Shreesha Srinath, Polychronis Xekalakis, Jose Renau, Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation. MICRO, 667-678, 2021.
Tyler Sorensen 0001, Lucas F. Salvador, Harmit Raval, Hugues Evrard, John Wickerson, Margaret Martonosi, Alastair F. Donaldson, Specifying and Testing GPU Workgroup Progress Models. CoRR abs/2109.06132, 2021.
Anna Jobin, Kingson Man, Antonio Damasio, Georgios Kaissis, Rickmer Braren, Julia Stoyanovich, Jay J. Van Bavel, Tessa V. West, Brent D. Mittelstadt 0002, Jason Eshraghian, Marta R. Costa-jussà, Asaf Tzachor, Aimun A. B. Jamjoom, Mariarosaria Taddeo, Edoardo Sinibaldi, Yipeng Hu, Miguel A. Luengo-Oroz, AI reflections in 2020. Nat. Mach. Intell. 3(1), 2-8, 2021.
Xiaoyuan Wang, Chenxi Jin, Jason Kamran Eshraghian, Herbert Ho-Ching Iu, Congying Ha, A Behavioral SPICE Model of a Binarized Memristor for Digital Logic Implementation. Circuits Syst. Signal Process. 40(6), 2682-2693, 2021.
Chandranil Chakraborttii, Heiner Litz, Reducing write amplification in flash by death-time prediction of logical block addresses. SYSTOR, 11:1-11:12, 2021.
Tanvir Ahmed Khan, Nathan Brown, Akshitha Sriraman, Niranjan K. Soundararajan, Rakesh Kumar 0003, Joseph Devietti, Sreenivas Subramoney, Gilles A. Pokam, Heiner Litz, Baris Kasikci, Twig: Profile-Guided BTB Prefetching for Data Center Applications. MICRO, 816-829, 2021.
Tyler Sorensen 0001, Lucas F. Salvador, Harmit Raval, Hugues Evrard, John Wickerson, Margaret Martonosi, Alastair F. Donaldson, Specifying and testing GPU workgroup progress models. Proc. ACM Program. Lang. 5(OOPSLA), 1-30, 2021.
Sung-Mo Steve Kang, Donguk Choi, Jason Kamran Eshraghian, Peng Zhou, Jieun Kim, Bai-Sun Kong, Xiaojian Zhu, Ahmet Samil Demirkol, Alon Ascoli, Ronald Tetzlaff, Wei D. Lu, Leon O. Chua, How to Build a Memristive Integrate-and-Fire Model for Spiking Neuronal Signal Generation. IEEE Trans. Circuits Syst. I Regul. Pap. 68(12), 4837-4850, 2021.
Colleen Josephson, Low-cost In-ground Soil Moisture Sensing with Radar Backscatter Tags. COMPASS, 299-311, 2021.
Xiaoyuan Wang, Zhiru Wu, Pengfei Zhou, Herbert H. C. Iu, Jason Kamran Eshraghian, Sung Mo Kang, FPGA Synthesis of Ternary Memristor-CMOS Decoders. CoRR abs/2104.10297, 2021.
Corey Lammie, Jason Kamran Eshraghian, Wei D. Lu, Mostafa Rahimi Azghadi, Memristive Stochastic Computing for Deep Learning Parameter Optimization. CoRR abs/2103.06506, 2021.
Xiaoyuan Wang, Pengfei Zhou, Jason Kamran Eshraghian, Chih-Yang Lin, Herbert Ho-Ching Iu, Ting-Chang Chang, Sung-Mo Steve Kang, High-Density Memristor-CMOS Ternary Logic Family. IEEE Trans. Circuits Syst. I Regul. Pap. 68(1), 264-274, 2021.
Max Ward 0001, Amitava Datta, Hung X. Nguyen, Jason Kamran Eshraghian, Efficient Network Analysis Under Link Deletion. CoRR abs/2108.06891, 2021.

2020

Scott Beamer, David Donofrio, Efficiently Exploiting Low Activity Factors to Accelerate RTL Simulation. DAC, 1-6, 2020.
Scott Beamer, A Case for Accelerating Software RTL Simulation. IEEE Micro 40(4), 112-119, 2020.
Daniel Petrisko, Chun Zhao, Scott Davidson, Paul Gao, Dustin Richmond, Michael Bedford Taylor, NoC Symbiosis : (Special Session Paper). NOCS, 1-8, 2020.
Saeed Kargar, Heiner Litz, Faisal Nawab, Predict and Write: Using K-Means Clustering to Extend the Lifetime of NVM Storage. CoRR abs/2011.02556, 2020.
Mostafa Rahimi Azghadi, Ying-Chen Chen, Jason Kamran Eshraghian, Jia Chen, Chih-Yang Lin, Amirali Amirsoleimani, Adnan Mehonic, Anthony J. Kenyon, Burt Fowler, Jack C. Lee, Yao-Feng Chang, Complementary Metal-Oxide Semiconductor and Memristive Hardware for Neuromorphic Computing. Adv. Intell. Syst. 2(5), 1900189, 2020.
Mostafa Rahimi Azghadi, Corey Lammie, Jason Kamran Eshraghian, Melika Payvand, Elisa Donati, Bernabé Linares-Barranco, Giacomo Indiveri, Hardware Implementation of Deep Network Accelerators Towards Healthcare and Biomedical Applications. CoRR abs/2007.05657, 2020.
Tyler Sorensen 0001, Aninda Manocha, Esin Tureci, Marcelo Orenes-Vera, Juan L. Aragón, Margaret Martonosi, A Simulator and Compiler Framework for Agile Hardware-Software Co-design Evaluation and Exploration. ICCAD, 97:1-97:9, 2020.
Mostafa Rahimi Azghadi, Ying-Chen Chen, Jason Kamran Eshraghian, Jia Chen, Chih-Yang Lin, Amirali Amirsoleimani, Adnan Mehonic, Anthony J. Kenyon, Burt Fowler, Jack C. Lee, Yao-Feng Chang, Complementary Metal-Oxide Semiconductor and Memristive Hardware for Neuromorphic Computing. Adv. Intell. Syst. 2(5), 2070050, 2020.
Nayana Prasad Nagendra, Grant Ayers, David I. August, Hyoun Kyu Cho, Svilen Kanev, Christos Kozyrakis, Trivikram Krishnamurthy, Heiner Litz, Tipp Moseley, Parthasarathy Ranganathan, AsmDB: Understanding and Mitigating Front-End Stalls in Warehouse-Scale Computers. IEEE Micro 40(3), 56-63, 2020.
Seungbum Baek, Jason Kamran Eshraghian, Wesley Thio, Yulia Sandamirskaya, Herbert H. C. Iu, Wei D. Lu, Live Demonstration: Video-to-Spike Conversion Using a Real-Time Retina Cell Network Simulator. AICAS, 131, 2020.
Jason Kamran Eshraghian, Qi Lin, Xiaoyuan Wang, Herbert H. C. Iu, Qing Hu 0004, Hao Tong, A Behavioral Model of Digital Resistive Switching for Systems Level DNN Acceleration. IEEE Trans. Circuits Syst. II Express Briefs 67-II(5), 956-960, 2020.
Opeoluwa Matthews, Aninda Manocha, Davide Giri, Marcelo Orenes-Vera, Esin Tureci, Tyler Sorensen 0001, Tae Jun Ham, Juan L. Aragón, Luca P. Carloni, Margaret Martonosi, The MosaicSim Simulator (Full Technical Report). CoRR abs/2004.07415, 2020.
Akash Sridhar, Nursultan Kabylkas, Jose Renau, Load Driven Branch Predictor (LDBP). CoRR abs/2009.09064, 2020.
Coen Arrow, Jason Kamran Eshraghian, Hancong Wu, Seungbum Baek, Herbert H. C. Iu, Kianoush Nazarpour, Live Demonstration: Prosthesis Control Using a Real-Time Retina Cell Network Simulator. ICECS, 1-2, 2020.
Dai Cheol Jung, Scott Davidson, Chun Zhao, Dustin Richmond, Michael Bedford Taylor, Ruche Networks: Wire-Maximal, No-Fuss NoCs : Special Session Paper. NOCS, 1-8, 2020.
Jason Eshraghian, Corey Lammie, Mostafa Rahimi Azghadi, Biologically Plausible Contrast Detection using a Memristor Array. ISCAS, 1-5, 2020.
Dan Iorga, Tyler Sorensen 0001, John Wickerson, Alastair F. Donaldson, Slow and Steady: Measuring and Tuning Multicore Interference. RTAS, 200-212, 2020.
Chandranil Chakraborttii, Heiner Litz, Improving the accuracy, adaptability, and interpretability of SSD failure prediction models. SoCC, 120-133, 2020.
Michael Bedford Taylor, Luis Vega, Moein Khazraee, Ikuo Magaki, Scott Davidson, Dustin Richmond, ASIC clouds: specializing the datacenter for planet-scale applications. Commun. ACM 63(7), 103-109, 2020.
Chandranil Chakraborttii, Heiner Litz, Learning I/O Access Patterns to Improve Prefetching in SSDs. ECML/PKDD (4), 427-443, 2020.
Jake Kirkham, Tyler Sorensen 0001, Esin Tureci, Margaret Martonosi, Foundations of empirical memory consistency testing. Proc. ACM Program. Lang. 4(OOPSLA), 226:1-226:29, 2020.
Colleen Josephson, Bradley Barnhart, Keith Winstein, Sachin Katti, Ranveer Chandra, Time-of-Flight Soil Moisture Estimation Using RF Backscatter Tags. IGARSS, 5049-5052, 2020.
Mostafa Rahimi Azghadi, Corey Lammie, Jason Kamran Eshraghian, Melika Payvand, Elisa Donati, Bernabé Linares-Barranco, Giacomo Indiveri, Hardware Implementation of Deep Network Accelerators Towards Healthcare and Biomedical Applications. IEEE Trans. Biomed. Circuits Syst. 14(6), 1138-1159, 2020.
Haven Blake Skinner, Rafael Trapani Possignolo, Sheng-Hong Wang, Jose Renau, LiveSim: A Fast Hot Reload Simulator for HDLs. ISPASS, 126-135, 2020.
Opeoluwa Matthews, Aninda Manocha, Davide Giri, Marcelo Orenes-Vera, Esin Tureci, Tyler Sorensen 0001, Tae Jun Ham, Juan L. Aragón, Luca P. Carloni, Margaret Martonosi, MosaicSim: A Lightweight, Modular Simulator for Heterogeneous Systems. ISPASS, 136-148, 2020.
Seungbum Baek, Jason Kamran Eshraghian, Wesley Thio, Yulia Sandamirskaya, Herbert H. C. Iu, Wei D. Lu, A Real-Time Retinomorphic Simulator Using a Conductance-Based Discrete Neuronal Network. AICAS, 79-83, 2020.
Jason Kamran Eshraghian, Human ownership of artificial creativity. Nat. Mach. Intell. 2(3), 157-160, 2020.
Tanvir Ahmed Khan, Akshitha Sriraman, Joseph Devietti, Gilles Pokam, Heiner Litz, Baris Kasikci, I-SPY: Context-Driven Conditional Instruction Prefetching with Coalescing. MICRO, 146-159, 2020.
Colleen Josephson, Bradley Barnhart, Sachin Katti, Keith Winstein, Ranveer Chandra, Demo Abstract: RF Soil Moisture Sensing via Radar Backscatter Tags. IPSN, 365-366, 2020.
Jason Kamran Eshraghian, Seungbum Baek, Timothée Levi, Takashi Kohno, Said F. Al-Sarawi, Philip H. W. Leong, Kyoung-Rok Cho, Derek Abbott, Omid Kavehei, Nonlinear retinal response modeling for future neuromorphic instrumentation. IEEE Instrum. Meas. Mag. 23(1), 21-29, 2020.
Andrew R. Henson, Tim Fiori, Ahmud Auleear, Iain C. McIntyre, Jason Eshraghian, A Transcranial Alternating Current Stimulator for Neural Entrainment. ISCAS, 1-5, 2020.
Heiner Litz, Milad Hashemi, Machine Learning for Systems. IEEE Micro 40(5), 6-7, 2020.
Sheng-Hong Wang, Rafael Trapani Possignolo, Haven Blake Skinner, Jose Renau, LiveHD: A Productive Live Hardware Development Flow. IEEE Micro 40(4), 67-75, 2020.
Grant Ayers, Heiner Litz, Christos Kozyrakis, Parthasarathy Ranganathan, Classifying Memory Access Patterns for Prefetching. ASPLOS, 513-526, 2020.
Ariful Azad, Mohsen Mahmoudi Aznaveh, Scott Beamer, Mark P. Blanco, Jinhao Chen, Luke D’Alessandro, Roshan Dathathri, Timothy A. Davis 0001, Kevin Deweese, Jesun Firoz, Henry A. Gabb, Gurbinder Gill, Bálint Hegyi, Scott P. Kolodziej, Tze Meng Low, Andrew Lumsdaine, Tugsbayasgalan Manlaibaatar, Timothy G. Mattson, Scott McMillan, Ramesh Peri, Keshav Pingali, Upasana Sridhar, Gábor Szárnyas, Yunming Zhang, Yongzhe Zhang, Evaluation of Graph Analytics Frameworks Using the GAP Benchmark Suite. IISWC, 216-227, 2020.

2019

Grant Ayers, Nayana Prasad Nagendra, David I. August, Hyoun Kyu Cho, Svilen Kanev, Christos Kozyrakis, Trivikram Krishnamurthy, Heiner Litz, Tipp Moseley, Parthasarathy Ranganathan, AsmDB: understanding and mitigating front-end stalls in warehouse-scale computers. ISCA, 462-473, 2019.
Nathan Chong, Tyler Sorensen 0001, John Wickerson, The Semantics of Transactions and Weak Memory in x86, Power, ARM, and C++. USENIX Annual Technical Conference, 2019.
Tyler Sorensen 0001, Sreepathi Pai, Alastair F. Donaldson, One Size Doesn’t Fit All: Quantifying Performance Portability of Graph Applications on GPUs. IISWC, 155-166, 2019.
Austin Rovinski, Chun Zhao, Khalid Al-Hawaj, Paul Gao, Shaolin Xie, Christopher Torng, Scott Davidson, Aporva Amarnath, Luis Vega, Bandhav Veluri, Anuj Rao, Tutu Ajayi, Julian Puscar, Steve Dai, Ritchie Zhao, Dustin Richmond, Zhiru Zhang, Ian Galton, Christopher Batten, Michael B. Taylor, Ronald G. Dreslinski, A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS. VLSI Circuits, 30-, 2019.
Tyler Sorensen 0001, Sreepathi Pai, Alastair F. Donaldson, Performance Evaluation of OpenCL Standard Support (and Beyond). IWOCL, 8:1-8:2, 2019.
Daphne I. Gorman, Rafael Trapani Possignolo, Jose Renau, EMI Architectural Model and Core Hopping. MICRO, 899-910, 2019.
Bin Wu, Matthew R. Guthaus, Bottom-Up Approach for High Speed SRAM Word-line Buffer Insertion Optimization. VLSI-SoC, 305-310, 2019.
Seungbum Baek, Jason Kamran Eshraghian, Sang-Hyun Ahn, Alex James 0001, Kyoung-Rok Cho, A Memristor-CMOS Braun Multiplier Array for Arithmetic Pipelining. ICECS, 735-738, 2019.
Riadul Islam, Matthew R. Guthaus, HCDN: Hybrid-Mode Clock Distribution Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(1), 251-262, 2019.
Jason Kamran Eshraghian, Sung-Mo Steve Kang, Seungbum Baek, Garrick Orchard, Herbert Ho-Ching Iu, Wen Lei, Analog Weights in ReRAM DNN Accelerators. AICAS, 267-271, 2019.
Ciyan Zheng, Jason Kamran Eshraghian, Alex James 0001, Herbert Ho-Ching Iu, Chaotic Oscillator Using Coupled Memristive Pairs. ICECS, 462-465, 2019.
Hunter Nichols, Michael Grimes, Jennifer Sowash, Jesse Cirimelli-Low, Matthew R. Guthaus, Automated Synthesis of Multi-Port Memories and Control. VLSI-SoC, 59-64, 2019.
Rafael Trapani Possignolo, Jose Renau, SMatch: Structural Matching for Fast Resynthesis in FPGAs. DAC, 75, 2019.
Yuanjiang Ni, Jishen Zhao, Heiner Litz, Daniel Bittman, Ethan L. Miller, SSP: Eliminating Redundant Writes in Failure-Atomic NVRAMs via Shadow Sub-Paging. MICRO, 836-848, 2019.
Ciyan Zheng, Dongsheng Yu, Herbert Ho-Ching Iu, Tyrone Fernando, Tingting Sun, Jason Kamran Eshraghian, Hengdao Guo, A Novel Universal Interface for Constructing Memory Elements for Circuit Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(12), 4793-4806, 2019.
Bin Wu, James E. Stine, Matthew R. Guthaus, Fast and Area-Efficient SRAM Word-Line Optimization. ISCAS, 1-5, 2019.
Colleen Josephson, Lei Yang 0031, Pengyu Zhang, Sachin Katti, Wireless computer vision using commodity radios. IPSN, 229-240, 2019.
Jaeheum Lee, Jason Kamran Eshraghian, Kyoung-Rok Cho, Kamran Eshraghian, Adaptive Precision CNN Accelerator Using Radix-X Parallel Connected Memristor Crossbars. CoRR abs/1906.09395, 2019.

2018

Tyler Sorensen 0001, Hugues Evrard, Alastair F. Donaldson, GPU Schedulers: How Fair Is Fair Enough?. CONCUR, 23:1-23:17, 2018.
Milad Hashemi, Kevin Swersky, Jamie A. Smith, Grant Ayers, Heiner Litz, Jichuan Chang, Christos Kozyrakis, Parthasarathy Ranganathan, Learning Memory Access Patterns. CoRR abs/1803.02329, 2018.
Ana Klimovic, Heiner Litz, Christos Kozyrakis, Selecta: Heterogeneous Cloud Storage Configuration for Data Analytics. USENIX Annual Technical Conference, 759-773, 2018.
Dustin Richmond, Alric Althoff, Ryan Kastner, Synthesizable Higher-Order Functions for C++. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(11), 2835-2844, 2018.
Samuel Grossman, Heiner Litz, Christos Kozyrakis, Making pull-based graph processing performant. PPoPP, 246-260, 2018.
Brennan Cain, Zain Merchant, Indira Avendano, Dustin Richmond, Ryan Kastner, PynqCopter - An Open-source FPGA Overlay for UAVs. IEEE BigData, 2491-2498, 2018.
Jason Kamran Eshraghian, Kyoung-Rok Cho, Ciyan Zheng, Minho Nam, Herbert Ho-Ching Iu, Wen Lei, Kamran Eshraghian, Neuromorphic Vision Hybrid RRAM-CMOS Architecture. IEEE Trans. Very Large Scale Integr. Syst. 26(12), 2816-2829, 2018.
Riadul Islam, Hany Ahmed Fahmy, Ping-Yao Lin, Matthew R. Guthaus, DCMCS: Highly Robust Low-Power Differential Current-Mode Clocking and Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 26(10), 2108-2117, 2018.
Milad Hashemi, Kevin Swersky, Jamie A. Smith, Grant Ayers, Heiner Litz, Jichuan Chang, Christos Kozyrakis, Parthasarathy Ranganathan, Learning Memory Access Patterns. ICML, 1924-1933, 2018.
Jason Kamran Eshraghian, Seungbum Baek, Jun-Ho Kim, Nicolangelo Iannella, Kyoung-Rok Cho, Yong-Sook Goo, Herbert H. C. Iu, Sung-Mo Steve Kang, Kamran Eshraghian, Formulation and Implementation of Nonlinear Integral Equations to Model Neural Dynamics Within the Vertebrate Retina. Int. J. Neural Syst. 28(7), 1850004:1-1850004:24, 2018.
Nathan Chong, Tyler Sorensen 0001, John Wickerson, The semantics of transactions and weak memory in x86, Power, ARM, and C++. PLDI, 211-225, 2018.
Dustin Richmond, Michael Barrow, Ryan Kastner, Everyone’s a Critic: A Tool for Exploring RISC-V Projects. FPL, 260-264, 2018.
Chandranil Chakraborttii, Vikas Sinha, Heiner Litz, SSD QoS Improvements through Machine Learning. SoCC, 511, 2018.
Dan Iorga, Tyler Sorensen 0001, Alastair F. Donaldson, Do Your Cores Play Nicely? A Portable Framework for Multi-core Interference Tuning and Analysis. CoRR abs/1809.05197, 2018.
Rafael Trapani Possignolo, Elnaz Ebrahimi 0001, Ehsan K. Ardestani, Alamelu Sankaranarayanan, José Luis Briz, Jose Renau, GPU NTC Process Variation Compensation With Voltage Stacking. IEEE Trans. Very Large Scale Integr. Syst. 26(9), 1713-1726, 2018.

2017

Daphne I. Gorman, Matthew R. Guthaus, Jose Renau, Architectural opportunities for novel dynamic EMI shifting (DEMIS). MICRO, 774-785, 2017.
Pengyu Zhang, Colleen Josephson, Dinesh Bharadia, Sachin Katti, FreeRider: Backscatter Communication Using Commodity Radios. CoNEXT, 389-401, 2017.
Rajsaktish Sankaranarayanan, Matthew R. Guthaus, Energy Savings and Performance Improvement in Subthreshold Using Adaptive Body Bias. ACM Great Lakes Symposium on VLSI, 431-434, 2017.
Scott Beamer, Krste Asanovic, David A. Patterson 0001, Reducing Pagerank Communication via Propagation Blocking. IPDPS, 820-831, 2017.
Tyler Sorensen 0001, Hugues Evrard, Alastair F. Donaldson, Cooperative kernels: GPU multitasking for blocking algorithms. ESEC/SIGSOFT FSE, 431-441, 2017.
Alastair F. Donaldson, Jeroen Ketema, Tyler Sorensen 0001, John Wickerson, Forward Progress on GPU Concurrency (Invited Talk). CONCUR, 1:1-1:13, 2017.
Aydin Buluç, Scott Beamer, Kamesh Madduri, Krste Asanovic, David A. Patterson 0001, Distributed-Memory Breadth-First Search on Massive Graphs. CoRR abs/1705.04590, 2017.
Elnaz Ebrahimi 0001, Rafael Trapani Possignolo, Jose Renau, Level shifter design for voltage stacking. ISCAS, 1-4, 2017.
Tyler Sorensen 0001, Hugues Evrard, Alastair F. Donaldson, Cooperative Kernels: GPU Multitasking for Blocking Algorithms (Extended Version). CoRR abs/1707.01989, 2017.
Jason Kamran Eshraghian, Kyoung-Rok Cho, Herbert H. C. Iu, Tyrone Fernando, Nicolangelo Iannella, Sung-Mo Steve Kang, Kamran Eshraghian, Maximization of Crossbar Array Memory Using Fundamental Memristor Theory. IEEE Trans. Circuits Syst. II Express Briefs 64-II(12), 1402-1406, 2017.
Elnaz Ebrahimi 0001, Matthew R. Guthaus, Jose Renau, Timing speculative SRAM. ISCAS, 1-4, 2017.
Ana Klimovic, Heiner Litz, Christos Kozyrakis, ReFlex: Remote Flash ≈ Local Flash. ASPLOS, 345-359, 2017.
Riadul Islam, Matthew R. Guthaus, CMCS: Current-Mode Clock Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 25(3), 1054-1062, 2017.
John Wickerson, Mark Batty, Tyler Sorensen 0001, George A. Constantinides, Automatically comparing memory consistency models. POPL, 190-204, 2017.
Nathan Chong, Tyler Sorensen 0001, John Wickerson, The Semantics of Transactions and Weak Memory in x86, Power, ARMv8, and C++. CoRR abs/1710.04839, 2017.
Dajung Lee, Alric Althoff, Dustin Richmond, Ryan Kastner, A streaming clustering approach using a heterogeneous system for big data analysis. ICCAD, 699-706, 2017.
Rafael Trapani Possignolo, Jose Renau, LiveSynth: Towards an Interactive Synthesis Flow. DAC, 74:1-74:6, 2017.
Haven Blake Skinner, Rafael Trapani Possignolo, Jose Renau, Liam: an actor based programming model for HDLs. MEMOCODE, 185-188, 2017.
Jason Kamran Eshraghian, Kyoung-Rok Cho, Seungbum Baek, Jun-Ho Kim, Kamran Eshraghian, Biological modeling of vertebrate retina: Rod cell to bipolar cell. TSP, 391-394, 2017.

2016

Tyler Sorensen 0001, Alastair F. Donaldson, The Hitchhiker’s Guide to Cross-Platform OpenCL Application Development. IWOCL, 2:1-2:12, 2016.
Rafael Trapani Possignolo, Elnaz Ebrahimi 0001, Haven Blake Skinner, Jose Renau, Fluid Pipelines: Elastic circuitry meets Out-of-Order execution. ICCD, 233-240, 2016.
Gabriel Southern, Jose Renau, Overhead of deoptimization checks in the V8 javascript engine. IISWC, 75-84, 2016.
Elnaz Ebrahimi 0001, Rafael Trapani Possignolo, Jose Renau, SRAM voltage stacking. ISCAS, 1634-1637, 2016.
Jason Kamran Eshraghian, Herbert H. C. Iu, Tyrone Fernando, Dongsheng Yu, Zhen Li 0004, Modelling and characterization of dynamic behavior of coupled memristor circuits. ISCAS, 690-693, 2016.
Matthew R. Guthaus, James E. Stine, Samira Ataei, Brian Chen, Bin Wu, Mehedi Sarwar, OpenRAM: an open-source memory compiler. ICCAD, 93, 2016.
Rafael Trapani Possignolo, Jose Renau, LiveSynth: Towards an interactive synthesis flow. Hot Chips Symposium, 1, 2016.
Heiner Litz, Benjamin Braun, David R. Cheriton, EXCITE-VM: Extending the Virtual Memory System to Support Snapshot Isolation Transactions. PACT, 401-412, 2016.
Ehsan K. Ardestani, Rafael Trapani Possignolo, José Luis Briz, Jose Renau, Managing Mismatches in Voltage Stacking with CoreUnfolding. ACM Trans. Archit. Code Optim. 12(4), 43:1-43:26, 2016.
Tyler Sorensen 0001, Alastair F. Donaldson, Mark Batty, Ganesh Gopalakrishnan, Zvonimir Rakamaric, Portable inter-workgroup barrier synchronisation for GPUs. OOPSLA, 39-58, 2016.
Sina Hassani, Gabriel Southern, Jose Renau, LiveSim: Going live with microarchitecture simulation. HPCA, 606-617, 2016.
Samira Ataei, James E. Stine, Matthew R. Guthaus, A 64 kb differential single-port 12T SRAM design with a bit-interleaving scheme for low-voltage operation in 32 nm SOI CMOS. ICCD, 499-506, 2016.
Tyler Sorensen 0001, Alastair F. Donaldson, Exposing errors related to weak memory in GPU applications. PLDI, 100-113, 2016.
Janarbek Matai, Dustin Richmond, Dajung Lee, Zac Blair, Qiongzhi Wu, Amin Abazari, Ryan Kastner, Resolve: Generation of High-Performance Sorting Architectures from High-Level Synthesis. FPGA, 195-204, 2016.
Jason Kamran Eshraghian, Seungbum Baek, Kyoung-Rok Cho, Nicolangelo Iannella, Jun-Ho Kim, Yong-Sook Goo, Herbert H. C. Iu, Tyrone Fernando, Kamran Eshraghian, Modelling and analysis of signal flow platform implementation into retinal cell pathway. APCCAS, 491-494, 2016.
Seungbum Baek, Jason Kamran Eshraghian, Kyoung-Rok Cho, Nicolangelo Iannella, Jun-Ho Kim, Herbert H. C. Iu, Tyrone Fernando, Kamran Eshraghian, Live demonstration: Signal flow platform implementation into retinal cell pathway. APCCAS, 740-741, 2016.
Dustin Richmond, Jeremy Blackstone, Matthew Hogains, Kevin Thai, Ryan Kastner, Tinker: Generating Custom Memory Architectures for Altera’s OpenCL Compiler. FCCM, 21-24, 2016.
Gabriel Southern, Jose Renau, Analysis of PARSEC workload scalability. ISPASS, 133-142, 2016.

2015

Madan Mohan Das, Gabriel Southern, Jose Renau, Section-Based Program Analysis to Reduce Overhead of Detecting Unsynchronized Thread Communication. ACM Trans. Archit. Code Optim. 12(2), 23:23:1-23:23:26, 2015.
Madan Mohan Das, Gabriel Southern, Jose Renau, Section based program analysis to reduce overhead of detecting unsynchronized thread communication. PPoPP, 283-284, 2015.
Riadul Islam, Hany Ahmed Fahmy, Ping-Yao Lin, Matthew R. Guthaus, Differential current-mode clock distribution. MWSCAS, 1-4, 2015.
Matthew Jacobsen, Dustin Richmond, Matthew Hogains, Ryan Kastner, RIFFA 2.1: A Reusable Integration Framework for FPGA Accelerators. ACM Trans. Reconfigurable Technol. Syst. 8(4), 22:1-22:23, 2015.
Scott Beamer, Krste Asanovic, David A. Patterson 0001, GAIL: the graph algorithm iron law. IA3@SC, 13:1-13:4, 2015.
Hany Ahmed Fahmy, Ping-Yao Lin, Riadul Islam, Matthew R. Guthaus, Switched capacitor quasi-adiabatic clocks. ISCAS, 1398-1401, 2015.
Jose Renau, Message from the program chair. ISPASS, vii, 2015.
Kyoung-Rok Cho, Sang-Jin Lee, Kamran Eshraghian, Memristor-CMOS logic and digital computational components. Microelectron. J. 46(3), 214-220, 2015.
Jade Alglave, Mark Batty, Alastair F. Donaldson, Ganesh Gopalakrishnan, Jeroen Ketema, Daniel Poetzl, Tyler Sorensen 0001, John Wickerson, GPU Concurrency: Weak Behaviours and Programming Assumptions. ASPLOS, 577-591, 2015.
Ping-Yao Lin, Hany Ahmed Fahmy, Riadul Islam, Matthew R. Guthaus, LC resonant clock resource minimization using compensation capacitance. ISCAS, 1406-1409, 2015.
Scott Beamer, Krste Asanovic, David A. Patterson 0001, The GAP Benchmark Suite. CoRR abs/1508.03619, 2015.
Benjamin M. LaCara, Ping-Yao Lin, Matthew R. Guthaus, Multi-frequency resonant clocks. ISCAS, 1402-1405, 2015.
Jade Alglave, Luc Maranget, Daniel Poetzl, Tyler Sorensen 0001, I compute, therefore I am (buggy): methodic doubt meets multiprocessors. Tiny Trans. Comput. Sci. 3, 2015.
Scott Beamer, Krste Asanovic, David A. Patterson 0001, Locality Exists in Graph Processing: Workload Characterization on an Ivy Bridge Server. IISWC, 56-65, 2015.
Riadul Islam, Matthew R. Guthaus, Low-Power Clock Distribution Using a Current-Pulsed Clocked Flip-Flop. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(4), 1156-1164, 2015.

2014

Riadul Islam, Matthew R. Guthaus, Current-mode clock distribution. ISCAS, 1203-1206, 2014.
Heiner Litz, David R. Cheriton, Amin Firoozshahian, Omid Azizi, John P. Stevenson, SI-TM: reducing transactional memory abort rates through snapshot isolation. ASPLOS, 383-398, 2014.
Kyoung-Rok Cho, Sang-Jin Lee, Omid Kavehei, Kamran Eshraghian, High Fill Factor Low-Voltage CMOS Image Sensor Based on Time-to-Threshold PWM VLSI Architecture. IEEE Trans. Very Large Scale Integr. Syst. 22(7), 1548-1556, 2014.
Janarbek Matai, Dustin Richmond, Dajung Lee, Ryan Kastner, Enabling FPGAs for the Masses. CoRR abs/1408.5870, 2014.
Heiner Litz, Ricardo J. Dias, David R. Cheriton, Efficient Correction of Anomalies in Snapshot Isolation Transactions. ACM Trans. Archit. Code Optim. 11(4), 65:1-65:24, 2014.
Bo Wang, Heiner Litz, David R. Cheriton, HICAMP bitmap: space-efficient updatable bitmap index for in-memory databases. DaMoN, 7:1-7:7, 2014.
Quentin Gautier, Alexandria Shearer, Janarbek Matai, Dustin Richmond, Pingfan Meng, Ryan Kastner, Real-time 3D reconstruction for FPGAs: A case study for evaluating the performance, area, and programmability trade-offs of the Altera OpenCL SDK. FPT, 326-329, 2014.
Amirkoushyar Ziabari, Je-Hyoung Park, Ehsan K. Ardestani, Jose Renau, Sung-Mo Kang, Ali Shakouri, Power Blurring: Fast Static and Transient Thermal Analysis Method for Packaged Integrated Circuits and Power Devices. IEEE Trans. Very Large Scale Integr. Syst. 22(11), 2366-2379, 2014.
Jeren Samandari-Rad, Matthew R. Guthaus, Richard Hughey, Confronting the Variability Issues Affecting the Performance of Next-Generation SRAM Design to Optimize and Predict the Speed and Yield. IEEE Access 2, 577-601, 2014.

2013

Alamelu Sankaranarayanan, Ehsan K. Ardestani, José Luis Briz, Jose Renau, An energy efficient GPGPU memory hierarchy with tiny incoherent caches. ISLPED, 9-14, 2013.
Matthew R. Guthaus, Gustavo Wilke, Ricardo Reis 0001, Revisiting automated physical synthesis of high-performance clock networks. ACM Trans. Design Autom. Electr. Syst. 18(2), 31:1-31:27, 2013.
Sang-Jin Lee, Kwang-Seok Oh, Yeon-Gyu Ahn, Kyoung-Rok Cho, Kamran Eshraghian, Complementary Resistive Switch (CRS) based smart sensor search engine. ISSNIP, 485-490, 2013.
Tyler Sorensen 0001, Ganesh Gopalakrishnan, Vinod Grover, Towards shared memory consistency models for GPUs. ICS, 489-490, 2013.
Scott Beamer, Krste Asanovic, David A. Patterson 0001, Direction-optimizing breadth-first search. Sci. Program. 21(3-4), 137-148, 2013.
Scott Beamer, Aydin Buluç, Krste Asanovic, David A. Patterson 0001, Distributed Memory Breadth-First Search Revisited: Enabling Bottom-Up Search. IPDPS Workshops, 1618-1627, 2013.
Ehsan K. Ardestani, Francisco J. Mesa-Martinez, Gabriel Southern, Elnaz Ebrahimi 0001, Jose Renau, Sampling in Thermal Simulation of Processors: Measurement, Characterization, and Evaluation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(8), 1187-1200, 2013.
Ehsan K. Ardestani, Gabriel Southern, Jason Doung, Elnaz Ebrahimi 0001, Jose Renau, ESESC: A fast performance, power, and temperature multicore simulator. Hot Chips Symposium, 1, 2013.
Sheldon Logan, Matthew R. Guthaus, Redundant C4 power pin placement to ensure robust power grid delivery. MWSCAS, 449-452, 2013.
Dustin Richmond, Ryan Kastner, Ali Irturk, John McGarry, A FPGA design for high speed feature extraction from a compressed measurement stream. FPL, 1-8, 2013.
Michael Chan, Heiner Litz, David R. Cheriton, Rethinking Network Stack Design with Memory Snapshots. HotOS, 2013.
Janusz Rajski, Miodrag Potkonjak, Adit D. Singh, Abhijit Chatterjee, Zain Navabi, Matthew R. Guthaus, Sezer Gören 0001, Embedded tutorials: Embedded tutorial 1: Cell-aware test-from gates to transistors. VLSI-SoC, 2013.
Sheldon Logan, Matthew R. Guthaus, A decap placement methodology for reducing joule heating and temperature in PSN interconnect. MWSCAS, 840-843, 2013.
Holger Fröning, Mondrian Nüssle, Heiner Litz, Christian Leber, Ulrich Brüning 0001, On Achieving High Message Rates. CCGRID, 498-505, 2013.
Ehsan K. Ardestani, Jose Renau, ESESC: A fast multicore simulator using Time-Based Sampling. HPCA, 448-459, 2013.

2012

Seokjoong Kim, Matthew R. Guthaus, Dynamic voltage scaling for SEU-tolerance in low-power memories. VLSI-SoC, 207-212, 2012.
Xuchu Hu, Walter James Condley, Matthew R. Guthaus, Library-aware resonant clock synthesis (LARCS). DAC, 145-150, 2012.
Seokjoong Kim, Matthew R. Guthaus, SEU-Aware Low-Power Memories Using a Multiple Supply Voltage Array Architecture. VLSI-SoC (Selected Papers), 181-195, 2012.
Matthew R. Guthaus, Welcome from the general chair. VLSI-SoC, 2012.
Jeren Samandari-Rad, Matthew R. Guthaus, Richard Hughey, VAR-TX: A variability-aware SRAM model for predicting the optimum architecture to achieve minimum access-time for yield enhancement in nano-scaled CMOS. ISQED, 506-515, 2012.
Haven Blake Skinner, Xuchu Hu, Matthew R. Guthaus, Harmonic resonant clocking. VLSI-SoC, 59-64, 2012.
Shoaib Kamil 0001, Derrick Coetzee, Scott Beamer, Henry Cook, Ekaterina Gonina, Jonathan Harper, Jeffrey Morlan, Armando Fox, Portable parallel performance from sequential, productive, embedded domain-specific languages. PPoPP, 303-304, 2012.
Xuchu Hu, Matthew R. Guthaus, Distributed LC Resonant Clock Grid Synthesis. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(11), 2749-2760, 2012.
Scott Beamer, Krste Asanovic, David A. Patterson 0001, Direction-optimizing breadth-first search. SC, 12, 2012.
Curtis Andrus, Matthew R. Guthaus, Lithography-aware layout compaction. ACM Great Lakes Symposium on VLSI, 147-152, 2012.
Matthew R. Guthaus, Baris Taskin, High-Performance, Low-Power Resonant Clocking: Embedded tutorial. ICCAD, 742-745, 2012.
Ehsan K. Ardestani, Elnaz Ebrahimi 0001, Gabriel Southern, Jose Renau, Thermal-aware sampling in architectural simulation. ISLPED, 33-38, 2012.
Sang-Jin Lee, Omid Kavehei, Kamran Eshraghian, Kyoung-Rok Cho, Live demonstration: High fill factor CIS based on single inverter architecture. ISCAS, 735, 2012.
Kamran Eshraghian, Omid Kavehei, Kyoung-Rok Cho, James M. Chappell, Azhar Iqbal, Said F. Al-Sarawi, Derek Abbott, Memristive Device Fundamentals and Modeling: Applications to Circuits and Systems Simulation. Proc. IEEE 100(6), 1991-2007, 2012.
Matthew R. Guthaus, Xuchu Hu, Gustavo Wilke, Guilherme Flach, Ricardo Reis 0001, High-performance clock mesh optimization. ACM Trans. Design Autom. Electr. Syst. 17(3), 33:1-33:17, 2012.
Rajsaktish Sankaranarayanan, Matthew R. Guthaus, A single-VDD ultra-low energy sub-threshold FPGA. VLSI-SoC, 219-224, 2012.

2011

Walter James Condley, Andrew W. Hill, Matthew R. Guthaus, Advanced logic design through hands-on digital music synthesis. MSE, 17-20, 2011.
Sheldon Logan, Matthew R. Guthaus, Package-chip co-design to increase flip-chip C4 reliability. ISQED, 553-558, 2011.
Xuchu Hu, Matthew R. Guthaus, Clock tree optimization for Electromagnetic Compatibility (EMC). ASP-DAC, 184-189, 2011.
Heiner Litz, Christian Leber, Benjamin Geib, DSL programmable engine for high frequency trading acceleration. WHPCF@SC, 31-38, 2011.
Xuchu Hu, Matthew R. Guthaus, Distributed Resonant clOCK grid Synthesis (ROCKS). DAC, 516-521, 2011.
Sangeetha Sudhakrishnan, Francisco J. Mesa-Martinez, Jose Renau, A design time simulator for computer architects. ISQED, 164-173, 2011.
Seokjoong Kim, Matthew R. Guthaus, SNM-aware power reduction and reliability improvement in 45nm SRAMs. VLSI-SoC, 204-207, 2011.
Omid Kavehei, Said F. Al-Sarawi, Kyoung-Rok Cho, Nicolangelo Iannella, Sung-Jin Kim, Kamran Eshraghian, Derek Abbott, Memristor-based Synaptic Networks and Logical Operations Using In-Situ Computing CoRR abs/1108.4182, 2011.
Matthew R. Guthaus, Distributed LC resonant clock tree synthesis. ISCAS, 1215-1218, 2011.
Omid Kavehei, Said F. Al-Sarawi, Kyoung-Rok Cho, Kamran Eshraghian, Derek Abbott, An Analytical Approach for Memristive Nanoarchitectures CoRR abs/1106.2927, 2011.
Kamran Eshraghian, Kyoung-Rok Cho, Omid Kavehei, Soon-Ku Kang, Derek Abbott, Sung-Mo Steve Kang, Memristor MOS Content Addressable Memory (MCAM): Hybrid Architecture for Future High Performance Search Engines. IEEE Trans. Very Large Scale Integr. Syst. 19(8), 1407-1417, 2011.
Jose Renau, Will Eatherton, Hot Chips 22. IEEE Micro 31(2), 4-5, 2011.
Sangeetha Sudhakrishnan, Rigo Dicochea, Jose Renau, Releasing efficient beta cores to market early. ISCA, 213-222, 2011.
Seokjoong Kim, Matthew R. Guthaus, Low-power multiple-bit upset tolerant memory optimization. ICCAD, 577-581, 2011.
Walter James Condley, Xuchu Hu, Matthew R. Guthaus, A methodology for local resonant clock synthesis using LC-assisted local clock buffers. ICCAD, 503-506, 2011.
Seokjoong Kim, Matthew R. Guthaus, Leakage-aware redundancy for reliable sub-threshold memories. DAC, 435-440, 2011.
Christian Leber, Benjamin Geib, Heiner Litz, High Frequency Trading Acceleration Using FPGAs. FPL, 317-322, 2011.
Michael Brown, Jose Renau, ReRack: power simulation for data centers with renewable energy generation. SIGMETRICS Perform. Evaluation Rev. 39(3), 77-81, 2011.

2010

Sang-Jin Lee, Omid Kavehei, Yoon-Ki Hong, Tae Won Cho, Younggap You, Kyoung-Rok Cho, Kamran Eshraghian, 3-D System-on-System (SoS) Biomedical-Imaging Architecture for Health-Care Applications. IEEE Trans. Biomed. Circuits Syst. 4(6), 426-436, 2010.
Matthew R. Guthaus, Gustavo Wilke, Ricardo Reis 0001, Non-uniform clock mesh optimization with linear programming buffer insertion. DAC, 74-79, 2010.
Walter James Condley, Xuchu Hu, Matthew R. Guthaus, Analysis of high-performance clock networks with RLC and transmission line effects. SLIP, 51-58, 2010.
Heiner Litz, Maximilian Thürmer, Ulrich Brüning 0001, TCCluster: A Cluster Architecture Utilizing the Processor Host Interface as a Network Interconnect. CLUSTER, 9-18, 2010.
Holger Fröning, Heiner Litz, Efficient hardware support for the Partitioned Global Address Space. IPDPS Workshops, 1-6, 2010.
Derek Chan, Matthew R. Guthaus, Analysis of power supply induced jitter in actively de-skewed multi-core systems. ISQED, 785-790, 2010.
Scott Beamer, Chen Sun 0003, Yong-Jin Kwon, Ajay Joshi, Christopher Batten, Vladimir Stojanovic, Krste Asanovic, Re-architecting DRAM memory systems with monolithically integrated silicon photonics. ISCA, 129-140, 2010.
Francisco J. Mesa-Martinez, Ehsan K. Ardestani, Jose Renau, Characterizing processor thermal behavior. ASPLOS, 193-204, 2010.

2009

Joseph Nayfach-Battilana, Jose Renau, SOI, interconnect, package, and mainboard thermal characterization. ISLPED, 327-330, 2009.
Michael Brown, Cyrus Bazeghi, Matthew R. Guthaus, Jose Renau, Measuring and modeling variabilityusing low-cost FPGAs. FPGA, 286, 2009.
Keven L. Woo, Matthew R. Guthaus, Fault-tolerant synthesis using non-uniform redundancy. ICCD, 213-218, 2009.
Scott Beamer, Krste Asanovic, Christopher Batten, Ajay Joshi, Vladimir Stojanovic, Designing multi-socket systems using silicon photonics. ICS, 521-522, 2009.
Heiner Litz, Holger Fröning, Ulrich Brüning 0001, A HyperTransport 3 Physical Layer Interface for FPGAs. ARC, 4-14, 2009.
Heiner Litz, Holger Fröning, Maximilian Thürmer, Ulrich Brüning 0001, An FPGA based verification platform for HyperTransport 3.x. FPL, 631-634, 2009.
Sang-Jin Lee, Kyung-Chang Park, Yeon-Ho Kim, Yun-ki Hong, Younggap You, Kyoung-Rok Cho, Tae Won Cho, Kamran Eshraghian, System-on-System (SoS) architecture for 3-D secure imaging. SoCC, 436-439, 2009.
Ajay Joshi, Christopher Batten, Yong-Jin Kwon, Scott Beamer, Imran Shamim, Krste Asanovic, Vladimir Stojanovic, Silicon-photonic clos networks for global on-chip communication. NOCS, 124-133, 2009.
Matthew R. Guthaus, Teaching VLSI design in 10 weeks. MSE, 41-44, 2009.
Holger Fröning, Heiner Litz, Ulrich Brüning 0001, Efficient Virtualization of High-Performance Network Interfaces. ICN, 434-439, 2009.

2008

Sangeetha Sudhakrishnan, Janaki T. Madhavan, E. James Whitehead Jr., Jose Renau, Understanding bug fix patterns in verilog. MSR, 39-42, 2008.
Sangeetha Sudhakrishnan, Liying Su, Jose Renau, Processor Verification with hwBugHunt. ISQED, 224-229, 2008.
Kamran Eshraghian, “Surfing the iSoC multitechnology platform: Volumetric growth beyond Moore’s law”. SoCC, 5-6, 2008.
Francisco J. Mesa-Martinez, Michael Brown, Joseph Nayfach-Battilana, Jose Renau, Measuring power and temperature from real processors. IPDPS, 1-5, 2008.
Matthew R. Guthaus, Dennis Sylvester, Richard B. Brown, Clock tree synthesis with data-path sensitivity matching. ASP-DAC, 498-503, 2008.
Heiner Litz, Holger Fröning, Mondrian Nüssle, Ulrich Brüning 0001, VELO: A Novel Communication Engine for Ultra-Low Latency Message Transfers. ICPP, 238-245, 2008.

2007

Francisco J. Mesa-Martinez, Jose Renau, Effective Optimistic-Checker Tandem Core Design through Architectural Pruning. MICRO, 236-248, 2007.
Cyrus Bazeghi, Francisco J. Mesa-Martinez, Jose Renau, System and Procesor Design Effort Estimation. VLSI-SoC (Selected Papers), 1-21, 2007.
Francisco J. Mesa-Martinez, Michael Brown, Joseph Nayfach-Battilana, Jose Renau, Measuring performance, power, and temperature from real processors. Experimental Computer Science, 16, 2007.
Cyrus Bazeghi, Francisco J. Mesa-Martinez, Brian Greskamp, Josep Torrellas, Jose Renau, Estimating design time for system circuits. VLSI-SoC, 60-65, 2007.
Francisco J. Mesa-Martinez, Joseph Nayfach-Battilana, Jose Renau, Power model validation through thermal measurements. ISCA, 302-311, 2007.

2006

Matthew R. Guthaus, Dennis Sylvester, Richard B. Brown, Process-induced skew reduction in nominal zero-skew clock trees. ASP-DAC, 84-89, 2006.
Kamran Eshraghian, SoC Emerging Technologies. Proc. IEEE 94(6), 1197-1213, 2006.
Yun Ding, Heiner Litz, Creating multiplatform user interfaces by annotation and adaptation. IUI, 270-272, 2006.
Chul Kim, A. M. Rassau, Stefan Lachowicz, Mike Myung-Ok Lee, Kamran Eshraghian, 3D-SoftChip: A Novel Architecture for Next-Generation Adaptive Computing Systems. EURASIP J. Adv. Signal Process. 2006, 2006.
Jose Renau, Karin Strauss, Luis Ceze, Wei Liu 0014, Smruti R. Sarangi, James Tuck, Josep Torrellas, Energy-Efficient Thread-Level Speculation. IEEE Micro 26(1), 80-91, 2006.
Matthew R. Guthaus, Dennis Sylvester, Richard B. Brown, Clock buffer and wire sizing using sequential programming. DAC, 1041-1046, 2006.
Wei Liu 0014, James Tuck, Luis Ceze, Wonsun Ahn, Karin Strauss, Jose Renau, Josep Torrellas, POSH: a TLS compiler that exploits program structure. PPoPP, 158-167, 2006.
Luis Ceze, Karin Strauss, James Tuck, Josep Torrellas, Jose Renau, CAVA: Using checkpoint-assisted value prediction to hide L2 misses. ACM Trans. Archit. Code Optim. 3(2), 182-208, 2006.
Francisco J. Mesa-Martinez, Michael C. Huang 0001, Jose Renau, SEED: scalable, efficient enforcement of dependences. PACT, 254-264, 2006.

2005

Jose Renau, James Tuck, Wei Liu 0014, Luis Ceze, Karin Strauss, Josep Torrellas, Tasking with out-of-order spawn in TLS chip multiprocessors: microarchitecture and compilation. ICS, 179-188, 2005.
Matthew R. Guthaus, Natesan Venkateswaran, Vladimir Zolotov, Dennis Sylvester, Richard B. Brown, Optimization objectives and models of variation for statistical gate sizing. ACM Great Lakes Symposium on VLSI, 313-316, 2005.
Rajiv A. Ravindran, Robert M. Senger, Eric D. Marsman, Ganesh S. Dasika, Matthew R. Guthaus, Scott A. Mahlke, Richard B. Brown, Partitioning Variables across Register Windows to Reduce Spill Code in a Low-Power Processor. IEEE Trans. Computers 54(8), 998-1012, 2005.
Cyrus Bazeghi, Francisco J. Mesa-Martinez, Jose Renau, uComplexity: Estimating Processor Design Effort. MICRO, 209-218, 2005.
Matthew R. Guthaus, Natesan Venkateswaran, Chandu Visweswariah, Vladimir Zolotov, Gate sizing using incremental parameterized statistical timing analysis. ICCAD, 1029-1036, 2005.
Chul Kim, A. M. Rassau, Stefan Lachowicz, Saeid Nooshabadi, Kamran Eshraghian, 3D-SoftChip: A Novel 3D Vertically Integrated Adaptive Computing System. VLSI-SoC, 71-86, 2005.
Jose Renau, Karin Strauss, Luis Ceze, Wei Liu 0014, Smruti R. Sarangi, James Tuck, Josep Torrellas, Thread-Level Speculation on a CMP can be energy efficient. ICS, 219-228, 2005.

2004

Seung-Min Lee, Stefan Lachowicz, David Lucas, A. M. Rassau, Kamran Eshraghian, Mike Myung-Ok Lee, Kamal E. Alameh, A Novel Design of Beam Steering n-phase OPTO-ULSI Processor for IIPS. DELTA, 395-402, 2004.
Kamal E. Alameh, Selam T. Ahderom, Mehrdad Raisi, Rong Zheng 0002, Kamran Eshraghian, MicroPhotonic Reconfigurable RF Signal Processor. DELTA, 63-70, 2004.
Selam T. Ahderom, Mehrdad Raisi, Kamal E. Alameh, Kamran Eshraghian, Testing and Analysis of Computer Generated Holograms for MicroPhotonic Devices. DELTA, 47-52, 2004.
Kamal E. Alameh, Kamran Eshraghian, Selam T. Ahderom, Mehrdad Raisi, Mike Myung-Ok Lee, Rainer Michalzik, Integrated MicroPhotonic Broadband Smart Antenna Beamformer. DELTA, 208-212, 2004.
Mehrdad Raisi, Selam T. Ahderom, Kamal E. Alameh, Kamran Eshraghian, Multi-band MicroPhotonic Tunable Optical Filter. DELTA, 391-394, 2004.
Luis Ceze, Karin Strauss, James Tuck, Jose Renau, Josep Torrellas, CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction. IEEE Comput. Archit. Lett. 3, 2004.
Chul Kim, Mike Myung-Ok Lee, Byung-Lok Cho, Kamran Eshraghian, SOC-B Design and Testing Technique of IS-95C CDMA Transmitter for Measurement of Electric Field Intensity using FPGA and ASIC. DELTA, 251-254, 2004.
Selam T. Ahderom, Mehrdad Raisi, Kamal E. Alameh, Kamran Eshraghian, Reconfigurable Add/Drop Multiplexing Topology Employing Adaptive MicroPhotonic Technology. HSNMC, 813-820, 2004.
Steven Hinckley, Paul V. Jansz-Drávetzky, Kamran Eshraghian, Pixel Structure Effects on Crosstalk in Backwall Illuminated CMOS Compatible Photodiode Arrays. DELTA, 53-58, 2004.
Seung-Min Lee, David Lucas, Mike Myung-Ok Lee, Kamran Eshraghian, Dae-Ik Kim, Kamal E. Alameh, High Density and Low Power Beam Steering Opto-ULSI Processor for IIPS. HSNMC, 894-902, 2004.
Yun Ding, Heiner Litz, Dennis Pfisterer, A graphical single-authoring framework for building multi-platform user interfaces. IUI, 235-237, 2004.
Kamal E. Alameh, Abdesselam Bouzerdoum, Selam T. Ahderom, Mehrdad Raisi, Kamran Eshraghian, X. Zhao, Rong Zheng 0002, Zhenglin Wang, Integrated MicroPhotonic Wideband RF Interference Mitigation Filter. DELTA, 387-390, 2004.
Mehrdad Raisi, Selam T. Ahderom, Kamal E. Alameh, Kamran Eshraghian, Dynamic MicroPhotonic WDM Equalizer. DELTA, 59-62, 2004.
Selam T. Ahderom, Mehrdad Raisi, Kamal E. Alameh, Kamran Eshraghian, Reconfigurable MicroPhotonic Add/Drop Multiplexer Architecture. DELTA, 203-207, 2004.
Zhenglin Wang, Kamal E. Alameh, Selam T. Ahderom, Rong Zheng 0002, Mehrdad Raisi, Kamran Eshraghian, Novel Integrated Optical Router for MicroPhotonic Switching. DELTA, 213-218, 2004.
Zhenglin Wang, Kamal E. Alameh, Selam T. Ahderom, Rong Zheng 0002, Mehrdad Raisi, Kamran Eshraghian, Integrated Optical Routing Topology for MicroPhotonic Switches. HSNMC, 848-854, 2004.

2003

Robert M. Senger, Eric D. Marsman, Michael S. McCorquodale, Fadi H. Gebara, Keith L. Kraver, Matthew R. Guthaus, Richard B. Brown, A 16-bit mixed-signal microsystem with integrated CMOS-MEMS clock reference. DAC, 520-525, 2003.
Basilio B. Fraguela, Jose Renau, Paul Feautrier, David A. Padua, Josep Torrellas, Programming the FlexRAM parallel intelligent memory system. PPoPP, 49-60, 2003.
Rajiv A. Ravindran, Robert M. Senger, Eric D. Marsman, Ganesh S. Dasika, Matthew R. Guthaus, Scott A. Mahlke, Richard B. Brown, Increasing the number of effective registers in a low-power processor using a windowed register file. CASES, 125-136, 2003.
Yun Ding, Heiner Litz, Rainer Malaka, Dennis Pfisterer, On Programming Information Agent Systems - An Integrated Hotel Reservation Service as Case Study. MATES, 50-61, 2003.
Michael C. Huang 0001, Jose Renau, Josep Torrellas, Positional Adaptation of Processors: Application to Energy Reduction. ISCA, 157-168, 2003.

2002

Michael C. Huang 0001, Jose Renau, Josep Torrellas, Energy-efficient hybrid wakeup logic. ISLPED, 196-201, 2002.
José F. Martínez, Jose Renau, Michael C. Huang 0001, Milos Prvulovic, Josep Torrellas, Cherry: checkpointed early resource recycling in out-of-order microprocessors. MICRO, 3-14, 2002.

2001

Michael C. Huang 0001, Jose Renau, Seung-Moon Yoo, Josep Torrellas, The Design of DEETM: a Framework for Dynamic Energy Efficiency and Temperature Management. J. Instr. Level Parallelism 3, 2001.
Michael C. Huang 0001, Jose Renau, Seung-Moon Yoo, Josep Torrellas, L1 data cache decomposition for energy efficiency. ISLPED, 10-15, 2001.
Maolin Tang, Kamran Eshraghian, Daryoush Habibi, Knowledge-based Genetic Algorithm for Layer Assignment. ACSC, 184-190, 2001.

2000

Morteza Biglari-Abhari, Kamran Eshraghian, Michael J. Liebelt, Improving Binary Compatibility in VLIW Machines through Compiler Assisted Dynamic Rescheduling. EUROMICRO, 1386-1393, 2000.
Kamran Eshraghian, Deep Submicron USLI Design Paradigm: Who is Writing the Future? ISQED, 213-, 2000.
Amine Bermak, Abdesselam Bouzerdoum, Kamran Eshraghian, A high fill-factor native logarithmic pixel: Simulation, design and layout optimization. ISCAS, 293-296, 2000.
Amine Bermak, Abdesselam Bouzerdoum, Kamran Eshraghian, Jean L. Noullet, CMOS circuit for high-speed flexible read-out of CMOS imagers. VCIP, 1471-1479, 2000.
Hon Nin Cheung, Li-Minn Ang, Kamran Eshraghian, Parallel Architecture for the Implementation of the Embedded Zerotree Wavelet Algorithm. ACAC, 3-8, 2000.
Li-Minn Ang, Hon Nin Cheung, Kamran Eshraghian, A dataflow-oriented VLSI architecture for a modified SPIHT algorithm using depth-first search bit stream processing. ISCAS, 291-294, 2000.
Michael C. Huang 0001, Jose Renau, Seung-Moon Yoo, Josep Torrellas, Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips. Intelligent Memory Systems, 152-159, 2000.
Michael C. Huang 0001, Jose Renau, Seung-Moon Yoo, Josep Torrellas, A framework for dynamic energy efficiency and temperature management. MICRO, 202-213, 2000.

1999

Li-Minn Ang, Hon Nin Cheung, Kamran Eshraghian, VLSI decoder architecture for embedded zerotree wavelet algorithm. ISCAS (1), 141-144, 1999.
Alexander Rassau, R. Mavaddat, Geoffrey Alagoda, Kamran Eshraghian, System analysis of an intelligent pixel mobile multimedia communicator. ISSPA, 801-804, 1999.
Li-Minn Ang, Hon Nin Cheung, Kamran Eshraghian, Robust image compression using the depth-first search on the wavelet zerotree. ISSPA, 797-800, 1999.
Stefan Lachowicz, Kamran Eshraghian, M. Hollreiser, Hans-Jörg Pfleiderer, Self-timed MESFET gallium arsenide circuit techniques for a direct digital frequency synthesiser. ISSPA, 575-578, 1999.
José Francisco López, Roberto Sarmiento, Antonio Núñez, Kamran Eshraghian, Stefan Lachowicz, Derek Abbott, Low Power Techniques for Digital GaAs VLSI. Great Lakes Symposium on VLSI, 321-324, 1999.
Hon Nin Cheung, Geoff Alagoda, Kamran Eshraghian, Li-Minn Ang, Smart pixel VLSI architecture for embedded zerotree wavelet coding. ISSPA, 693-696, 1999.
Li-Minn Ang, Hon Nin Cheung, Kamran Eshraghian, EZW algorithm using depth-first representation of the wavelet zerotree. ISSPA, 75-78, 1999.
Saeid Nooshabadi, Juan A. Montiel-Nelson, Kamran Eshraghian, A novel latch design technique for high speed GaAs circuits. ICECS, 331-334, 1999.
Alexander Rassau, Geoffrey Alagoda, Kamran Eshraghian, Massively parallel wavelet based video codec for an intelligent-pixel mobile multimedia communicator. ISSPA, 793-795, 1999.
Stefan Lachowicz, Kamran Eshraghian, Hans-Jörg Pfleiderer, Self-Timed Techniques for Low-Power Digital Arithmetic in GaAs VLSI. VLSI, 245-256, 1999.
A. M. Rassau, Geoffrey Alagoda, David Lucas, J. Austin-Crowe, Kamran Eshraghian, Massively Parallel Intelligent Pixel Implementation of a Zerotree Entropy Video Codec for Multimedia Communications. VLSI, 89-100, 1999.
Maolin Tang, Kamran Eshraghian, Hon Nin Cheung, An Efficient Aopproach to Constrained Via Minimization for Two-Layer VLSI Routing. ASP-DAC, 149-152, 1999.

1998

Kamran Eshraghian, Design methodology and performance estimation for complementary gallium arsenide. ICECS, 379-383, 1998.
A. M. Rassau, T. C. B. Yu, H. Cheung, Stefan Lachowicz, Kamran Eshraghian, William A. Crossland, Tim D. Wilkinson, Smart Pixel Implementation of a 2-D Parallel Nucleic Wavelet Transform for Mobile Multimedia Communications. DATE, 191-195, 1998.
Ganesh Kothapalli, Stefan Lachowicz, Kamran Eshraghian, A parameter search technique to build an ARMA model. KES (1), 298-301, 1998.
Derek Abbott, Said F. Al-Sarawi, B. Gonzalez, José Francisco López, J. Austin-Crowe, Kamran Eshraghian, Neu-MOS (νMOS) for smart sensors and extension to a novel neu-GaAs (νGaAs) paradigm. ICECS, 397-404, 1998.

1997

Alireza Moini, Abdesselam Bouzerdoum, Kamran Eshraghian, Andre Yakovleff, Xuan Thong Nguyen, Andrew J. Blanksby, Richard Beare, Derek Abbott, Robert Eugene Bogner, An insect vision-based motion detection chip. IEEE J. Solid State Circuits 32(2), 279-284, 1997.
Kamran Eshraghian, Opto-VLSI Systems for Multimedia Computing. VLSI Design, 6-9, 1997.
Kamran Eshraghian, Juan A. Montiel-Nelson, Saeid Nooshabadi, An Asynchronous Morphological Processor for Multi-Media Applications. VLSI Design, 336-341, 1997.
Nozar Tabrizi, Michael J. Liebelt, Kamran Eshraghian, A Tabular Method for Guard Strengthening, Symmetrization, and Operator Reduction for Martin’s Asynchronous Design Methodology. IEEE Trans. Computers 46(9), 1050-1054, 1997.
José Francisco López, Roberto Sarmiento, Kamran Eshraghian, Antonio Núñez, Noise margin enhancement in GaAs ROM’s using current mode logic. IEEE J. Solid State Circuits 32(4), 592-597, 1997.
José Francisco López, Kamran Eshraghian, Roberto Sarmiento, Antonio Núñez, Derek Abbott, GaAs pseudodynamic latched logic for high performance processor cores. IEEE J. Solid State Circuits 32(8), 1297-1303, 1997.

1996

Nozar Tabrizi, Michael J. Liebelt, Kamran Eshraghian, Delay Hazards in Complex Gate Based Speed Independent VLSI Circuits. Great Lakes Symposium on VLSI, 266-271, 1996.
Nozar Tabrizi, Michael J. Liebelt, Kamran Eshraghian, Dynamic hazards and speed independent delay model. ASYNC, 94-103, 1996.

1995

Song Cui, Neil Burgess, Michael J. Liebelt, Kamran Eshraghian, A GaAs IEEE Floating Point Standard Single Precision Multiplier. IEEE Symposium on Computer Arithmetic, 91-97, 1995.
Derek Abbott, Andre Yakovleff, Alireza Moini, X. Thong Nguyen, Andrew J. Blanksby, Richard Beare, Andrew Beaumont-Smith, Gyudong Kim, Abdesselam Bouzerdoum, Robert E. Bogner, Kamran Eshraghian, Biologically inspired obstacle avoidance - a technology independent paradigm. Mobile Robots, 2-12, 1995.
Song Cui, Neil Burgess, Michael J. Liebelt, Kamran Eshraghian, A 32-bit GaAs IEEE floating point multiplier using Trailing-1’s rounding algorithm. Electronic Technology Directions, 246-252, 1995.
Zhihong Man, X. H. Yu, Kamran Eshraghian, Marimuthu Palaniswami, A robust adaptive sliding mode tracking control using an RBF neural network for robotic manipulators. ICNN, 2403-2408, 1995.
Alireza Moini, Kamran Eshraghian, Abdesselam Bouzerdoum, The impact of VLSI technologies on neural networks. ICNN, 158-163, 1995.
X. Thong Nguyen, Abdesselam Bouzerdoum, Robert E. Bogner, Alireza Moini, Kamran Eshraghian, Feature Representation of Motion Trajectories. ICNN, 2922-2927, 1995.
Alireza Moini, Andrew J. Blanksby, Abdesselam Bouzerdoum, Kamran Eshraghian, Richard Beare, Multiplicative noise cancellation (MNC) in analog VLSI vision sensors. Electronic Technology Directions, 253-257, 1995.
Zhihong Man, Hong Ren Wu, Kamran Eshraghian, Marimuthu Palaniswami, An adaptive tracking controller using neural networks for nonlinear systems. ICNN, 314-319, 1995.

1994

Andre Yakovleff, X. Thong Nguyen, Abdesselam Bouzerdoum, Alireza Moini, Robert E. Bogner, Kamran Eshraghian, Dual-Purpose Interpretation of Sensory Information. ICRA, 1635-1640, 1994.
Roberto Sarmiento, Kamran Eshraghian, Implementation of a CORDIC Processor for CFFT Computation in Gallium Arsenide Technology. EDAC-ETC-EUROASIC, 238-244, 1994.